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A cell degradation design rule specifies the maximum capacitive load a cell can drive without causing cell performance degradation during the fall transition.

But I don’t know the difference between cell degradation and max capacitance constraint rule:(

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Virtual clock feature:

• A clock that is not connected to any port or pin within the current design
• Serves as a reference for input or output delays

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Continue reading “difference between real clock and ideal clock”

Ideal Network Feature:

• No DRC (capacitance, fanout, and transition) check for ideal net.
• Zero pin capacitance and net capacitance for timing calculation.

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Clock Latency contain following two parts:

• Network Latency: net delay from clock port to flip-flop clock pin in the design.
• Source Latency:   delay from clock source to design clock port.

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Continue reading “Definition of Timing Path”

http://www.mydigit.cn/mydisktest.htm

优盘检测软件，
现在奸商一堆，就连可爱的calf也中招了，所以大家还是多个心眼，买到U盘后检测一下。

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utf8编码的中文分词词库下载
http://cn.minidx.com/index.php?option=com_docman&task;=doc_download&gid;=47

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Feature of ideal clock:

• Infinite drive capability
• Zero rise/fall transition times
• Zero skew
• Zero insertion delay or latency

For ideal network feature: http://vlsi-concept.blogspot.com/2008/12/ideal-network-feature.html
Continue reading “Ideal Clock Feature”

概览

==, !=, >, < , >=, < =, =~, !~ 解释

== 等于
!= 不等于
>  大于
<  小于
>= 大于等于
< = 小于等于
=~ 匹配
!~ 不匹配

Continue reading “filter_collection 可以使用的操作符”