Virtual clock feature:
- A clock that is not connected to any port or pin within the current design
- Serves as a reference for input or output delays
difference between real clock and ideal clock
Ideal Network Feature
Ideal Network Feature:
- No DRC (capacitance, fanout, and transition) check for ideal net.
- Zero pin capacitance and net capacitance for timing calculation.
Clock Latency
Clock Latency contain following two parts:
- Network Latency: net delay from clock port to flip-flop clock pin in the design.
- Source Latency: delay from clock source to design clock port.
Definition of Timing Path
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Ideal Clock Feature
Feature of ideal clock:
- Infinite drive capability
- Zero rise/fall transition times
- Zero skew
- Zero insertion delay or latency
For ideal network feature: http://vlsi-concept.blogspot.com/2008/12/ideal-network-feature.html
Continue reading “Ideal Clock Feature”
filter_collection 可以使用的操作符
概览
==, !=, >, < , >=, < =, =~, !~ 解释
== 等于
!= 不等于
> 大于
< 小于
>= 大于等于
< = 小于等于
=~ 匹配
!~ 不匹配
Continue reading “filter_collection 可以使用的操作符”
difference between dc_shell and dc_shell-t
The "-t" extension invokes DC shell in Tcl-mode, which is the
recommended mode, and by default, also XG mode, which is also
recommended. Design Vision is ONLY available in TCL mode, hence no
"-t" extension is needed, and it also comes up in XG mode by default.
Continue reading “difference between dc_shell and dc_shell-t”