Acronyms in ASIC Design

The chipmakers use many technical terms in their day to day work, but in abbreviated forms. Beginners find it difficult to get along with these abbreviations unlike others. The Saint gathered and created a glossary of many acronyms that are frequently used in IC design industry.

The chipmakers use many technical terms in their day to day work, but in abbreviated forms. Beginners find it difficult to get along with these abbreviations unlike others. The Saint gathered and created a glossary of many acronyms that are frequently used in IC design industry.

ALD
Atomic Layer Deposition
AOCV
Advanced On-Chip Variation
ASIC
Application-Specific Integrated Circuit
ATPG
Automatic Test Pattern Generation
BC
Best-Case
BEOL
Back-End-Of-Line
C4
Controlled Collapse Chip Connection
CAD
Computer-Aided Design
CDC
Clock Domain Crossing
CCS
Composite Current Source
CMP
Chemical Mechanical Planarization
CSP
Chip Scale Package
CTS
Clock Tree Synthesis
CVD
Chemical Vapor Deposition
DEF
Design Exchange Format
DFM
Design For Manufacturability
DFT
Design For Test
DRAM
Dynamic Random Access Memory
DRC
Design Rule Check
ECD
Electrochemical Deposition
ECO
Engineering Change Order
EDA
Electronic Design Automation
EM
Electromigration
ERC
Electrical Rule Check
ESD
Electro-Static Discharge
FEOL
Front-End-Of-Line
FPGA
Field Programmable Gate Array
GDSII
Graphic Database System II
HDL
Hardware Description Language
IC
Integrated Circuit
ILM
Interface Logic Model
LEC
Logic Equivalence Check
LEF
Library Exchange Format
LOCV
Location-based On-Chip Variation
LSI
Large-Scale Integration
LVS
Layout Versus Schematic
MBE
Molecular Beam Epitaxy
MSI
Medium-Scale Integration
MCMM
Multi-Corner Multi-Mode
NDR
Non-Default Rules
NLDM
Non-Linear Delay Model
OASIS
Open Artwork System Interchange Standard
OCV
On-Chip Variation
OPC
Optical Proximity Correction
PCB
Printed Circuit Board
PMU
Power Management Unit
PVD
Physical Vapor Deposition
PVT
Process Voltage Temperature
RAM
Random Access Memory
RDL
Re-Distribution Layer
ROM
Read Only Memory
RTA
Rapid Thermal Anneal
RTL
Register Transfer Level
SDC
Synopsys Design Constraint
SDF
Standard Delay Format
SI
Signal Integrity
SiP
System in Package
SoC
System on Chip
SPEF
Standard Parasitic Exchange Format
SPICE
Simulation Program with Integrated Circuit Emphasis
SSI
Small-Scale Integration
SSN
Simultaneous Switching Noise
STA
Static Timing Analysis
ULSI
Ultra-Large-Scale Integration
UPF
Unified Power Format
VHDL
VHSIC hardware description language
VHSIC
Very-High-Speed Integrated Circuits
VLSI
Very-Large-Scale Integration
WC
Worst-Case

P.S: Though significant efforts have been put in gathering all the possible acronyms, the saint could have still missed out some. If you can think of any, which are missing in the above list, please write to the saint so that he can update his list.

参考:

  • http://siliconsaint.blogspot.com/2012/07/acronyms-in-asic-design_21.html

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