ASIC Design Flow In Brief

  1. chip specification;
  2. front end modeling, use C, C++ or System C/system verilog to do the modeling and simulation;
  3. design implementation in front end, verilgo or VHDL ;
  4. simulation;
  5. FPGA verification(optional);
  6. Synthesis, Design compiler , RTL to gate level netlist;
  7. Physical implementation.

    1. chip specification;
    2. front end modeling, use C, C++ or System C/system verilog to do the modeling and simulation;
    3. design implementation in front end, verilgo or VHDL ;
    4. simulation;
    5. FPGA verification(optional);
    6. Synthesis, Design compiler , RTL to gate level netlist;
    7. Physical implementation.
    8. Post simulation ( simulation with back-annotate SDF)
    9. signoff ( StarRCXT, PrimeTime, Hercules).
    10. set data to foundry ( GDSII file ), OPC.
    11. manufacturing.
    12. Test and packaging.

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