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  • strict warning: Only variables should be passed by reference in /var/www/truevue.org/sites/all/themes/zeropoint/template.php on line 341.
  • strict warning: Only variables should be passed by reference in /var/www/truevue.org/sites/all/themes/zeropoint/template.php on line 341.
  • strict warning: Only variables should be passed by reference in /var/www/truevue.org/sites/all/themes/zeropoint/template.php on line 341.
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  • strict warning: Non-static method view::load() should not be called statically in /var/www/drupal_module/views/views.module on line 906.
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2009年半导体产业二十大预言 zz

新年快乐!2009年到来了,在目前不确定的经济形势下,电子产业的变化才刚刚开始。与往年一样,EETimes将于大家分享对于全球半导体产业市场情况的预测。

产业预言者对于2009年及之后的半导体产业和集成电路制造设备市场的整体前景有多种不同的观点。为了帮助大家梳理市场的混乱,我将与大家分享我自己对于2009年的芯片以及其他市场的预测。

1. 低迷还是衰退?

我非常荣幸能看到其他预测者对于2009年的看法。我认为,他们中的大多数都太乐观了。不幸的是,我能预见的是在2009的IC产业出现25%的衰退,这个相比2001年的大萧条只是好了一点点。然而感觉起来将比2001年更遭。

How to check the library (lib) belong to which .db file

Use link command to see those information:

icc_shell> link

  Linking design 'ChipTop'
  Using the following designs and libraries:
  --------------------------------------------------------------------------

Channel-width Based Leakage Power Calculation

cost of leakage:

Min (ΣWvth1∗Cvth1+ΣWvth2∗Cvth2+…)

Footprint Optimization

What's footprint?

Footprint is a attribute of library cells. It's provide by by vendors.
See following library cell information (log of report_lib):

How to read ITF file to find the process technology

The MinWidth of POLY layer represent the process technology.

See following example:

What does '45-nm' mean

So today, "65 nm" or "45 nm" doesn't exactly refer to the line width, and certainly doesn't indicate how closely you can pack transistors together, although it does provide some indication of these things. Still, it is probably most accurate to say that the number is simply the name of the process, rather than the measure of any particular feature.

Cell Degradation Design Rule

The standard design rules (max_transition, max_fanout, and max_capacitance) cannot account for all reliability issues in deep submicron technologies.A new design rule was introduced to model this behavior more accurately.

Timing Arc

Timing Arc Definition:

Timing arcs, along with netlist interconnect information, are the paths followed by the path tracer during path analysis.

Each timing arc has a startpoint and an endpoint.

cell degradation

A cell degradation design rule specifies the maximum capacitive load a cell can drive without causing cell performance degradation during the fall transition.

But I don't know the difference between cell degradation and max capacitance constraint rule:(

Virtual Clock

Virtual clock feature:

  • A clock that is not connected to any port or pin within the current design
  • Serves as a reference for input or output delays