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IC Design

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For more VLSI information, please visit http://www.pythonclub.org/vlsi/start

ILM (Interface Logic Model ) basic flow using ICC

ILM stands for Interface Logic Model.
In a hierarchical design, we usually convert sub-module to ILM block during implementation.
Following flow is an example of create ILM block using Synopsys IC Compiler(ICC):

Net delay in ICC timing report

Net delay in ICC timing report is displayed in the input pin connected to the net.
 


U3249/y (buf_d10w) 20.3900 42.7837 86.3139 r
n3002 (net) 1 11.0479 0.0000 86.3139 r
U3250/a (buf_d2m_hvt) 20.3900 0.4279 * 86.7417 r

Physical Design Rule

What's Physical Design Rule

 

1. Interface between the circuit designer and process engineer
2. Guidelines for constructing process masks
3. Unit dimension: minimum line width
 
scalable design rules: lambda parameter
absolute dimensions: micron rules
 
4. Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur
5. A complete set includes
set of layers
intra-layer: relations between objects in the same layer
inter-layer: relations between objects on different layers
 

ASIC Design Implementation Flow In Brief

  1. design setup;
  2. floorplan;
  3. placement;
  4. Clock Tree synthesis (CTS);
  5. routing;
  6. chip finishing( insert diode, insert filler, insert metal filler, add redundant via …);
  7. signoff flow ( StarRCXT, PT, DRC, LVS).

ASIC Design Flow In Brief

  1. chip specification;
  2. front end modeling, use C, C++ or System C/system verilog to do the modeling and simulation;
  3. design implementation in front end, verilgo or VHDL ;
  4. simulation;
  5. FPGA verification(optional);
  6. Synthesis, Design compiler , RTL to gate level netlist;
  7. Physical implementation.

Mapping File: Database Layer <==> Process Layer

Maps File:
    Map database layers to process layers conducting_layers, via_layers, marker_layers, remove_layers.

Layer Information:
    Resistance information is optional: RPSQ (for conductors) or RPV (for vias) overrides process file, if specified

Interconnect Technology File (ITF)

What’s ITF:

ITF stands for Interconnect Technology File.
It contains a description of the process cross-section and connectivity section.
It describes the thicknesses and physical attributes of the conductor and dielectric layers.
It used to extract RC value for the chip.
It can be used to generate TLU TLUPlus files.
ITF file example http://gudonghua.googlepages.com/itf-file-example.itf.txt

Design Rule Checking (DRC)

There are two DRC, logic DRC & physical DRC:

Logic DRC contain following three points:

  1. Net fanout
  2. Net capacitance
  3. Net transition

Physical DRC contain various rule, and it's depends on technology, it is described in technology file (tf file), tf file example http://gudonghua.googlepages.com/tf-file-example.tf.txt.

MCMM: Multi-Corner Multi-Mode

What's MCMM

MCMM stands for: Multi-Corner Multi-Mode (static timing analysis used in the design of digital ICs)

履霜,坚冰至!我们何去何从?-------详解目前半导体业危机及对策 zz

但是,大家有没有真正清楚的把整件事情想清楚,可怕的不是这次危机本身,可怕的是你在这次危机中迷茫而失去信心。

所以我写这个帖子来帮助大家思考,给出我自己的答案,当然你也可以有你的答案,大家尽管在回复中发表意见,非常欢迎不同见解。