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IC Design

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For more VLSI information, please visit http://www.pythonclub.org/vlsi/start

独立承当65nm的ASIC项目

下周就要开始独立承当一个ASIC项目了,4年前进入EDA行业,去年转到Backend Design。 也不为啥,就为了一探Design的究竟,揭开Design的神秘面纱了。

VCD File In Power Analysis

VCD Stands for Value Change Dump, VCD file is used for verilog simulation and power analysis.

Tap Cell

1. What is a 'tap cell'

The basic idea with a global substrate tap methodology is to omit internal substrate taps from the standard cells and instead to sprinkle dedicated tap cells throughout the P&R layout.  The process design rules require that no piece of source/drain diffusion (inside a standard cell) be more than some maximum distance away from the tap diffusion inside at least one of the sprinkled tap cells.

IC Complier Placement and Optimization Attributes

Attribute Coarse placement Detail placement Optimization
is_fixed Cannot move cells Cannot move cells Cannot move, rotate, or resize cells

cts_fixed
(imposed on clock
buffers by clock tree synthesis)

Cannot move cells Cannot move cells Cannot move, rotate, or resize cells
is_soft_fixed Cannot move cells No restrictions No restrictions
size_only No restrictions No restrictions Can only resize cells
in_place_size_only Cannot move cells No restrictions Can only resize cells if there is room
dont_touch No restrictions No restrictions Cannot move, rotate, or resize cells

Gate-Array-Backfill (GBF) Cells

Nearly every chip being produced today faces at least one respin in the life of the project. Multiple respins are not uncommon. The financial pain of these engineering potholes can be alleviated by changing as few layers in the design as possible--two layers changed in a 10 layer design is a great savings over an all-layer respin.

DCAP(Decap) cells

Instantaneous Voltage Drop (IVD) is a part of the landscape in Deep Sub-Micron (DSM) design. IVD is a droop in rail voltage prompted by large amounts of simultaneous switching in a circuit. Problems with IVD are especially common to high speed memories, which have potentially thousands of cells switching at a time.

Clock Net Shielding In IC Compiler (ICC)

Overview of Clock Net Shielding Methodologies

There are 2 clock net shielding flow, the difference is clock net shielding is either before signal routing or post. You can use the following two shielding methodologies:

  1. Shield before signal route: routing clocks + shielding clock nets + routing signal nets
  2. Shield after signal route: routing clocks + routing signal nets + shielding clock nets

锁相环PLL(Phase Locked Loop)

什么是锁相环PLL(Phase Locked Loop):

锁相环PLL是指一种电路或者模块,它用于在通信的接收机中,其作用是对接收到的信号进行处理,并从其中提取某个时钟的相位信息。或者说,对于接收到的信号,仿制一个时钟信号,使得这两个信号从某种角度来看是同步的(或者说,相干的)。

Data-to-Data Setup/Hold Check

Data-to-Date Setup Check:

A data-to-data setup check specifies how early the constrained signal (the "-to" or pin) must arrive relative to the related pin (the "-from" pin). It is specified in terms of a positive leading offset relative to the related pin - this means positive values indicate a leftward, or "leading," direction on a waveform diagram. If the constrained signal arrives too late relative to the check, it will fail.

Formality Equivalence Checking Verification Process

What is Formal Verification?

Formal verification is an alternative to verification through simulation. Verification through simulation applies a large number of input vectors to the circuit and then compares the resulting output vectors to expected values. As designs become larger and more complex and require more simulation vectors, regression testing with traditional simulation tools becomes a bottleneck in the design flow.