Cln40g SVT NMOS Temperature Inversion Effect

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We have temperature inversion effect in 40nm and below technology. At 65nm hand early technology, the worst timing corner are alway low voltage, high temperature corener. But in 40nm and below, the timing worst corner is at low voltage, cold temperature. This is the  Temperature Inversion Effect.

Temperature effect

Following are 2 main affect while Temperature increase:

  • Vth decreases & (Vgs–Vth) increases as T increases.
  • Mobility decreases as T increases

In 65nm and above, the mobility is dominate the current/timing. While in 40nm and below technology, at low voltage situation, Vth became the main part of current/timing.

As a result we got the temperature inversion effect.

Vth & Temperature Curve

Vth & Temperature Curve

Mobility & Temperature

Mobility Temperature

Invert Delay vs. Temperature

Invert Delay vs. Temperature

参考:

http://www.eetimes.com/design/embedded/4231192/Dealing-with-multi-Vt---m...

http://www.edaboard.com/thread162095.html