Synchronizer is a special logic in ASIC design. In phsysical design, synchronizer pair need to be placed together.
Why do we need to synchronize signals at all? Signals arriving unrelated to the sampling clock might violate setup or hold conditions thus driving the output of the capturing flip-flop into a meta-stable state, or simply put, undefined. This means we could not guarantee the validity of the data at the output of the flip-flop. We do know, that since a flip-flop is a bi-stable device – after some (short) time the output will resolve either a logic “0″ or a logic “1″. The basic idea is to block the undefined (or meta-stable) value during this settling time from propagating into the rest of the circuit and creating havoc in our state machines. The simplest implementation is to use a shift register construction as pictured.
We must remember, that regardless of the input transition, a meta-stable signal can resolve to either a logic “0″ or a logic “1″ after the settling time. The picture below is almost identical to the first, but here capture FF1 settled into a logic ’0″ state. On the next clk B rising edge it will capture a static “1″ value and thus change. Compare the timing of capture FF1 and capture FF2 in both diagrams. We see there is an inherent uncertainty on when capture FF2 assumes the input data. This uncertainty is one clk B period for the given synchronizer circuit.
Sometimes, the uncertainty described can hurt the performance of a system. A trick which I don’t see used so often, is to use the falling edge triggered flop as one of the capture flops. This reduces the uncertainty from 1-2 capturing clock cycles to 1-1.5 capturing clock cycles. Sometimes though, there is no meaning to this uncertainty, it becomes more meaningful when there is only a phase difference between the 2 clock domains