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IC Design

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Combinational Logic Snake Paths

周一, 12/05/2011 - 21:49 — 东华

When using spyglass to do netlist audit, there is a rule called HiDeFCombLogicSnakePath. For backend design, it's better avoid snake paths in the design. And what's a snake path?

Add Overlay Cell in RedHawk

周三, 11/30/2011 - 10:35 — 东华

In the past weeks, I use Apache RedHawk to do power analysis. Just finished top power analysis with overlay cell. Take down the steps to include overlay cell into Redhawk power analysis.

LEF/DEF Language Reference

周一, 11/28/2011 - 17:06 — 东华

LEF & DEF are common use files in IC design. For most EDA tools, LEF & DEF files are standard interface files. You can write your design to def & lef, and import it in other tools.

独立承当65nm的ASIC项目

周日, 11/27/2011 - 11:27 — 东华

下周就要开始独立承当一个ASIC项目了，4年前进入EDA行业，去年转到Backend Design。 也不为啥，就为了一探Design的究竟，揭开Design的神秘面纱了。

VCD File In Power Analysis

周四, 09/08/2011 - 13:22 — admin

VCD Stands for Value Change Dump, VCD file is used for verilog simulation and power analysis.

Tap Cell

周四, 09/02/2010 - 08:52 — admin

1. What is a 'tap cell'

The basic idea with a global substrate tap methodology is to omit internal substrate taps from the standard cells and instead to sprinkle dedicated tap cells throughout the P&R layout.  The process design rules require that no piece of source/drain diffusion (inside a standard cell) be more than some maximum distance away from the tap diffusion inside at least one of the sprinkled tap cells.

IC Complier Placement and Optimization Attributes

周二, 08/10/2010 - 15:31 — admin
Attribute Coarse placement Detail placement Optimization
is_fixed Cannot move cells Cannot move cells Cannot move, rotate, or resize cells

cts_fixed
(imposed on clock
buffers by clock tree synthesis)

 Cannot move cells Cannot move cells Cannot move, rotate, or resize cells
is_soft_fixed Cannot move cells No restrictions No restrictions
size_only No restrictions No restrictions Can only resize cells
in_place_size_only Cannot move cells No restrictions Can only resize cells if there is room
dont_touch No restrictions No restrictions Cannot move, rotate, or resize cells

Gate-Array-Backfill (GBF) Cells

周三, 08/04/2010 - 22:48 — admin

Nearly every chip being produced today faces at least one respin in the life of the project. Multiple respins are not uncommon. The financial pain of these engineering potholes can be alleviated by changing as few layers in the design as possible--two layers changed in a 10 layer design is a great savings over an all-layer respin.

DCAP(Decap) cells

周三, 08/04/2010 - 22:32 — admin

Instantaneous Voltage Drop (IVD) is a part of the landscape in Deep Sub-Micron (DSM) design. IVD is a droop in rail voltage prompted by large amounts of simultaneous switching in a circuit. Problems with IVD are especially common to high speed memories, which have potentially thousands of cells switching at a time.

Clock Net Shielding In IC Compiler (ICC)

周五, 07/30/2010 - 18:25 — admin

Overview of Clock Net Shielding Methodologies

There are 2 clock net shielding flow, the difference is clock net shielding is either before signal routing or post. You can use the following two shielding methodologies:

  1. Shield before signal route: routing clocks + shielding clock nets + routing signal nets
  2. Shield after signal route: routing clocks + routing signal nets + shielding clock nets